Recent wiring substrates, on which semiconductor chips are mounted, have been miniaturized and increased in density and are handled in the form of a large wiring substrate that includes a plurality of wiring substrate units. Japanese Laid-Open Patent Publication Nos. 2009-194321 and 2005-252155 describes examples of such wiring substrates.
As illustrated in FIG. 16, a large wiring substrate 100 includes a plurality of (here, nine) wiring substrate units 101 and a frame 102 which surrounds the wiring substrate units 101. When cut at cutting positions A10, the wiring substrate 100 is singulated into individual wiring substrate units 101.
Each wiring substrate unit 101 includes an identification mark 103 which is identified as a particular character or a particular symbol in a plan view. In FIG. 16, nine identification marks 103 are identified as “B1” to “B9” in a plan view. Each identification mark 103 indicates position information or lot information of the wiring substrate unit 101.
The identification marks 103 are formed, for example, by boring through holes in the insulation layer and forming a plating layer in the through holes. The through holes are arranged to form a particular shape (e.g., “B1”) that is identifiable in a plan view.